Communication systems commonly divide transmitted data into frames, with various forms of control information inserted in or between the frames to ensure that the transmitter and receiver are synchronized. For example, in the IEEE 802.3ba standard for 40 gigabits per second (Gbps) and 100 Gbps Ethernet physical layer, data is transferred using multiple parallel data lanes. Data can arrive at the receiver with some relative timing offset (“skew”) between the data lanes. Accordingly, control information in the form of alignment markers (AMs) are inserted periodically into the data stream to allow the receiver to find frame boundaries on each data lane and then remove the skew between data lanes so that the data can be recovered correctly. The IEEE 802.3bj standard defines forward error correction (FEC) features for use on in the 40 Gbps/100 Gbps Ethernet physical layer over backplanes and copper cables. In FEC data lanes, the AMs have the same format as data lanes without FEC defined in 802.3ba, but are distributed in a different pattern within the transmitted frames.
The standard method for locating AMs in a data stream is to perform a bitwise correlation operation at each location where an AM might be located, searching for a known bit pattern. With high bit-rates, such as 100 Gbps, this correlation operation is not straightforward. Either a very large number of correlation circuits is required, operating in parallel, or else a smaller number (perhaps a single correlator) can be swept across the data until alignment is found. Both approaches have disadvantages. With a large bank of parallel correlators, alignment is quick (e.g., around 200 ρs), but has a high cost in terms of silicon area and power consumption. With a single correlator, silicon cost and power consumption are low, but alignment can be slow (e.g., on the order of 10 ms worst case).